----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 10/25/2021 09:53:49 AM
-- Design Name: 
-- Module Name: counter_example - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter_example is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           data : out STD_LOGIC_VECTOR (3 downto 0));
end counter_example;

architecture Behavioral of counter_example is

signal count : unsigned(3 downto 0);
signal count1 : unsigned(31 downto 0);
signal en : std_logic;

begin

-- delilnik ure
process (clk)
begin
   if (clk'event and clk = '1') then
      if reset = '1' then
            count1 <= (others => '0');
            en <= '0';
      elsif count1 = 100000000 then
            en <= '1';
            count1 <= (others => '0');
      else
            count1 <= count1 + 1;
            en <= '0';
      end if;
   end if;
end process;

-- osnovni stevec
process (clk)
begin
   if (clk'event and clk = '1') then
      if reset = '1' then
            count <= (others => '0');
      else
            if(en = '1') then
                count <= count + 1;
            end if;
      end if;
   end if;
end process;


data <= std_logic_vector(count);

end Behavioral;